AI-agent MCP server for FPGA design: compile, validate & generate Verilog from C⏚ HDL.
Neosyn-fpga-mcp is an MCP integration. AI-agent MCP server for FPGA design: compile, validate & generate Verilog from C⏚ HDL.
The published pypi package is neosyn-fpga-mcp, version 1.4.0. Its declared MCP transport is stdio.
The package declares CG_JAR: Path to the C⏚ compiler jar (cg-language-server.jar). Download the prebuilt jar from the cg-compiler GitHub releases..
Check the maintainer’s instructions for account access, authentication and the supported client configuration. Once connected, inspect the tools your client receives and try a small task that matches the server’s stated purpose. The registry description does not include a verified, complete tool list.
View the publisher’s registry entry · Project repository. This profile uses version 1.4.0 from the registry. Registration identifies the publisher namespace; it does not establish that this is a first-party integration for every service it connects.
Browse related other integrations MCP servers for tools that cover the same kind of work.
| Variable | Description | Required |
|---|---|---|
| CG_JAR | Path to the C⏚ compiler jar (cg-language-server.jar). Download the prebuilt jar from the cg-compiler GitHub releases. | Optional |
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